Ameer M.S. Abdelhadi

Research Scientist / Hardware-Efficient Machine Learning
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Ontario, M5S 3G4 Canada

e-mail:  ameer DOT abdelhadi AT utoronto DOT ca
LinkedIn | GitHub | Scholar





Open Source

Open Source Contribution

Available online at my GitHub repository:

All contributions are licensed under the BSD 3-Clause ("BSD New" or "BSD Simplified") license.

Open Source IPs

Note: All packages are composed of a fully parameterized, modular and generic Verilog implementation of the proposed IP, together with other approaches. A run-in-batch simulate and synthesize flow manager is also provided.
  • Modular SRAM-based Indirectly Indexed Ternary Content-Addressable Memory (II-BCAM). [Code: GitHub]
    Published in FCCM'15. [Paper: PDF, DOI] [Talk: PDF, PPT]
  • Deep and Narrow Binary Content-Addressable Memories using FPGA-based BRAMs. [Code: GitHub]
    Published in FPT'14. [Paper: PDF, DOI] [Poster: PDF, VSD]
  • Modular SRAM-based Indirectly Indexed Longest Prefix Match Ternary Content-Addressable Memory (LPM II-TCAM). [Code: GitHub]
    Pending conference publication.
  • A Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs. [Code: GitHub]
    Pending conference publication.
  • Modular Switched Multi-ported SRAM-based Memories. [Code: GitHub]
    Published in TRETS special issue, 2016. [Paper: PDF]
  • Modular Multi-Ported SRAM-based Memories. [Code: GitHub]
    Published in FPGA'14. [Paper: PDF, DOI] [Talk: PDF, PPT]
  • Run-time programmable frequency clocks using Altera PLLs. [Code: GitHub]
    Used in FCCM'13 paper [Paper: PDF, DOI] [Talk: PDF, PPT],
    and FPT'12 paper [Paper: PDF, DOI] [Poster: PDF, VSD].
  • Cell-based mixed-timing FIFOs - RTL to GDS design framework. [Code: GitHub]
    Pending journal publication. Also, appeared in ICCAD'12 workshop. [Poster: PDF, VSD]
  • Linear Feedback Shift Register (LFSR); A periodic counter with random count. [Code: GitHub]
  • Binary-to-BCD-Converter Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm. [Code: GitHub]

Open Source CAD Tools

  • LUT Input Permutations Enumerator. [Code: GitHub]
    Published in ReConfig'11. [Paper: PDF, DOI] [Talk: PDF, PPT]
  • Simulated Annealing Cell-Based Placer. [Code: GitHub]
  • Multi-Sink Lee-Moore Shortest Path Maze Router. [Code: GitHub]
  • Multi-Fanout Kernighan-Lin Hypergraph Bi-Partitioning. [Code: GitHub]
  • Timing-Driven Variation-Aware Clock Mesh Synthesis Environment [Code: GitHub]
    Published in GLSVLSI'10. [Paper: PDF, DOI] [Talk: PDF, PPT]
  • Geometric CAD Algorithms for Physical Design of VLSI Layout:
    • Cell-based VLSI Layout Vompaction Algorithm Based on a Modified Segments Tree Data Structure ; Programmed in Perl Script. [Code: GitHub]
    • Polygonal VLSI Layout Layer Arithmetic Operations Based on a Modified Segments Tree Data Structure for Finding the Contour of Union of Rectangles ; Programmed in Perl Script. [Code: GitHub]

Last updated October 2020.
Copyright © 2020 Ameer M.S. Abdelhadi. All rights reserved.