#!/bin/csh -f

####################################################################################
## Copyright (c) 2014, University of British Columbia (UBC)  All rights reserved. ##
##                                                                                ##
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## modification,  are permitted  provided that  the following conditions are met: ##
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##   * Redistributions  in  binary  form  must  reproduce  the  above   copyright ##
##     notice, this  list  of  conditions  and the  following  disclaimer in  the ##
##     documentation and/or  other  materials  provided  with  the  distribution. ##
##   * Neither the name of the University of British Columbia (UBC) nor the names ##
##     of   its   contributors  may  be  used  to  endorse  or   promote products ##
##     derived from  this  software without  specific  prior  written permission. ##
##                                                                                ##
## THIS  SOFTWARE IS  PROVIDED  BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ##
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####################################################################################

####################################################################################
##                     Run-in-batch Simulation  Flow Manager                      ##
##                                                                                ##
##    Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com)    ##
##     SRAM-based BCAM; The University of British Columbia (UBC), April 2014      ##
####################################################################################

####################################################################################
## USAGE:                                                                         ##
##   ./sim <Pattern width List> <CAM depth list> <#Cycles> <Verbose?>             ##
##                                                                                ##
## - Use comma delimited lists; no space; can be surrounded by brackets ()[]{}<>. ##
## - CAM depth (k-lines), pattern width (9-bits) & #cycles are positive integers. ##
## - Verbose? (Binary; 0/1)                                                       ##
##                                                                                ##
## EXAMPLES:                                                                      ##
## ./sim 1 8 1000000 1                                                            ##
##    Simulate 1M cycles of a 8K lines CAM, 9 bits pattern width ,verbosed.       ##
## ./sim 4,8 2,4 1000000 0                                                        ##
##    Simulate 1M cycles of CAMs with 2k or 4k lines, 36, 73, not verbosed.       ##
##                                                                                ##
## The following files and directories will be created after simulation :         ##
##   - sim.res : A list of simulation results, each run in a separate line,       ##
##               including all design styles.                                     ##
####################################################################################

# setup environment variables and Altera's CAD tools 
# change file to your own flow if necessary 
source ./altera.13.1.csh

# require exactly 4 arguments
if (${#argv} != 4) then
    printf '\x1b[%i;3%im' 1 1
    printf 'Error: Exactly 4 are required\n'
    printf '\x1b[0m'
    goto errorMessage
endif

# convert each argument list into a c-shell list (remove commas and etc.)
set PATWLST = (`echo ${argv[1]} | tr ",()[]{}<>" " "`)
set CAMDLST = (`echo ${argv[2]} | tr ",()[]{}<>" " "`)
set SCYCNUM = ${argv[3]}
set VERBOSE = ${argv[4]}

# check arguments correctness (positive integer numbers)
foreach ARGVAL ($CAMDLST $PATWLST $SCYCNUM)
  set ARGVALIsNumber=`echo $ARGVAL | egrep -c '^[0-9]+$'`
  if ($ARGVALIsNumber != 1) then
    printf '\x1b[%i;3%im' 1 1
    printf "Error (${ARGVAL}): Pattern width, CAM depth and number of cycles arguments should be possitive integers\n"
    printf '\x1b[0m'
    goto errorMessage
  endif
end

# check verbose argument correctness
if ( ($VERBOSE != 0) & ($VERBOSE != 1) ) then
  printf '\x1b[%i;3%im' 1 1
  printf "Error (${VERBOSE}): Verbose argument should be a binary; 0 or 1\n"
  printf '\x1b[0m'
  goto errorMessage
endif

# total different fifo designs
@ FlowOprNum = ((${#CAMDLST})*(${#PATWLST}))
@ FlowOprCnt = 0

printf '\x1b[%i;3%im' 7 4
printf "= Simulate in batch with the following parameters:\n"
printf "= CAM Depth          : $CAMDLST\n"
printf "= Pattern width      : $PATWLST\n"
printf "= Simulation Cycles  : $SCYCNUM\n"
printf "= Verbose            : $VERBOSE\n"
printf '\x1b[0m'

# operate on all different RAM parameters

foreach CURPATW ($PATWLST)
  foreach CURCAMD ($CAMDLST)

    @ FlowOprCnt++

    printf '\x1b[%i;3%im' 7 2
    printf "\n== Starting Simulation (${FlowOprCnt}/${FlowOprNum}): [CAM depth:${CURCAMD}; Pattern width:${CURPATW}; Simulation cycles:${SCYCNUM}]\n"
    printf '\x1b[0m'

    # remove work directory to recompile verilog
    if (-d work) \rm -rf work
    # recreate work directory
    vlib work

    # run current simulation
    vlog -work work +define+SIM+VERBOSE=$VERBOSE+CYCC=$SCYCNUM+CDEP=$CURCAMD+PWID=$CURPATW+PIPE=0+REGI=0+REGO=0 utils.vh bcam_bhv.v pe_bhv.v camctl.v dpmlab.v mwm20k.v setram.v idxram.v vacram.v iitram9bx1k.v iitram9b.v ii2dcam9b.v ii2dcam.v ii2dcam_tb.v
    vsim -c -L altera_mf_ver -L lpm_ver -L altera_ver -L stratixv_ver -do "run -all" ii2dcam_tb

    printf '\x1b[%i;3%im' 7 2
    printf "== Simulation (${FlowOprCnt}/${FlowOprNum}) Completed: [CAM depth:${CURCAMD}; Pattern width:${CURPATW}; Simulation cycles:${SCYCNUM}]\n"
    printf '\x1b[0m'

  end
end

# clean unrequired files / after run
if (-d work      ) \rm -rf work
if (-e transcript) \rm -f  transcript

goto scriptEnd

# error message
errorMessage:
printf '\x1b[%i;3%im' 1 1
cat << EOH
USAGE:
  ./sim <Pattern width List> <CAM depth list> <#Cycles> <Verbose?>
- Use comma delimited lists; no space; can be surrounded by brackets ()[]{}<>.
- CAM depth (k-lines), pattern width (9-bits) & #cycles are positive integers.
- Verbose? (Binary; 0/1)
EXAMPLES:
./sim 1 8 1000000 1
   Simulate 1M cycles of a 8K lines CAM, 9 bits pattern width ,verbosed.
./sim 4,8 2,4 1000000 0
   Simulate 1M cycles of CAMs with 2k or 4k lines, 36, 73, not verbosed.
The following files and directories will be created after simulation :
  - sim.res : A list of simulation results, each run in a separate line,
              including all design styles.
EOH
printf '\x1b[0m'
scriptEnd:
